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UML based reverse engineering for the verification of railway control logics
Linnaeus University, Faculty of Technology, Department of computer science and media technology (CM).ORCID iD: 0000-0002-2833-7196
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2007 (English)In: Proceedings of International Conference on Dependability of Computer Systems, DepCoS-RELCOMEX 2006, 2007, p. 3-10Conference paper, Published paper (Refereed)
Abstract [en]

The Unified Modeling Language (UML) is widely used as a high level object oriented specification language. In this paper we present a novel approach in which reverse engineering is performed using UML as the modelling language used to achieve a representation of the implemented system. The target is the core logic of a complex critical railway control system, which was written in an application specific legacy language. UML perfectly suited to represent the nature of the core logic, made up by concurrent and interacting processes, using a bottom-up approach and proper modeling rules. Each process, in fact, was strictly related to the management of a physically (resp. logically) well distinguished railway device (resp. functionality). The obtained model deeply facilitated the static analysis of the logic code, allowing for at a glance verification of correctness and compliance with higher-level specifications, and opened the way to refactoring and other formal analyses. © 2006 IEEE.

Place, publisher, year, edition, pages
2007. p. 3-10
Keywords [en]
Computer simulation languages, Logic programming, Railroad traffic control, Unified Modeling Language, Verification, Bottom up approach, Legacy language, Logic code, Railway control systems, Reverse engineering
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:lnu:diva-73694DOI: 10.1109/DEPCOS-RELCOMEX.2006.55Scopus ID: 2-s2.0-34848906245ISBN: 0769525652 ISBN: 9780769525655 OAI: oai:DiVA.org:lnu-73694DiVA, id: diva2:1213845
Conference
International Conference on Dependability of Computer Systems, DepCoS-RELCOMEX 2006, 25 May 2006 through 27 May 2006, Szklarska Poreba
Note

Conference code: 70338; Cited By :9; Export Date: 26 April 2018; Conference Paper; Correspondence Address: Abbaneo, C.; ANSALDO SIGNAL - Ansaldo Segnalamento Ferroviario S.p.A., RAMS Division, Via Nuova delle Brecce 260, Naples, Italy; email: abbaneo.chiara@asf.ansaldo.it; References: Bondavalli, A., Fantechi, A., Latella, D., Simoncini, L., Design Validation of Embedded Dependable Systems (2001) IEEE Micro, 21 (5), pp. 52-62; Cimatti, A., Formal Verification of a Railway Interlocking System using Model Checking (1998) Formal Aspects of Computing, 10 (4), pp. 361-380; Egyed, A., Medvidovic, N., Consistent Architectural Refinement and Evolution using the Unified Modeling Language (2001) Proceedings of ICSE, pp. 83-87. , Toronto, Canada, May; CENELEC: EN 50126 Railways Applications - The specification and demonstration of Reliability, Maintainability and Safety (RAMS); Cung, A., Lee, Y.S., Reverse Software Engineering with UML for website maintenance (2000) IEEE Proceedings of Working Conference in Reverse Engineering '00, pp. 100-111; Chikofsky, E.J., Cross, J.H., Reverse Engineering and Design Recovery: A Taxonomy (1990) IEEE Software, 7 (1). , January; De Nicola, G., di Tommaso, P., Esposito, R., Flammini, F., Marmo, P., Orazzo, A., A Grey Box Approach to the Functional Testing of Complex Automatic Train Protection Systems (2005) LNCS, 3463, pp. 305-317. , Springer-Verlag Heidelberg; Fowler, M., (1999) Refactoring: Improving the Design of Existing Code, , Addison-Wesley Professional, 1st edition; OMG website, , http://www.omg.org/uml; http://www.rational.com, Rational Corporation website; UNISIG ERTMS/ETCS - Class 1 Issue 2.2.2 Subset 026; Heath, W.S., (1991) Real-Time Software Techniques, , Van Nostrand Reinhold, New York

Available from: 2018-06-05 Created: 2018-06-05 Last updated: 2018-06-05

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Flammini, Francesco

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