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  • 1.
    Bassoo, Vandana
    et al.
    Victoria University, Australia.
    Tom, K
    Victoria University, Australia.
    Mustafa, A. K.
    Victoria University, Australia.
    Cijvat, Ellie
    Lunds Universitet.
    Sjöland, Henrik
    Lunds Universitet.
    Faulkner, Mike
    Victoria University, Australia.
    Potential Architecture for Future Generation "Green" Wireless Base Station2009In: 2009 4th International Symposium on Wireless and Pervasive Computing, ISWPC 2009, IEEE, 2009, article id 4800602Conference paper (Refereed)
    Abstract [en]

    Current radio frequency power amplifiers (PAs) in 3G base stations have very high power consumption leading to a hefty cost and negative environmental impact. In this paper, we propose a potential architecture design for future wireless base station. Issues associated with components of the architecture are investigated. A comparison of PA with pulse width modulation drive and PA with envelope elimination and restoration (EER) drive is offered. EER-driven PA promises high efficiency over a wide dynamic range but has bandwidth expansion problems. A novel approach which reduces bandwidth expansion on the envelope by 54% is proposed. A modulator is used to convert amplitude and phase information into the edges of a pulse train. The modulator also eradicates some analog components present in traditional base station design.

  • 2.
    Bassoo, Vandana
    et al.
    Victoria University, Australia.
    Tom, Kevin
    Victoria University, Australia.
    Mustafa, A. K.
    Victoria University, Australia.
    Cijvat, Ellie
    Lund University.
    Sjöland, Henrik
    Lund University.
    Faulkner, Mike
    Victoria University; Australia.
    A potential transmitter architecture for future generation green wireless base station2009In: EURASIP Journal on Wireless Communications and Networking, ISSN 1687-1472, E-ISSN 1687-1499, article id 821846Article in journal (Refereed)
    Abstract [en]

    Current radio frequency power amplifiers in 3G base stations have very high power consumption leading to a hefty cost and negative environmental impact. In this paper, we propose a potential architecture design for future wireless base station. Issues associated with components of the architecture are investigated. The all-digital transmitter architecture uses a combination of envelope elimination and restoration (EER) and pulse width modulation (PWM)/pulse position modulation (PPM) modulation. The performance of this architecture is predicted from the measured output power and efficiency curves of a GaN amplifier. 57% efficiency is obtained for an OFDM signal limited to 8 dB peak to average power ratio. The PWM/PPM drive signal is generated using the improved Cartesian sigma delta techniques. It is shown that an RF oversampling by a factor of four meets the WLAN spectral mask, and WCDMA specification is met by an RF oversampling of sixteen.

  • 3.
    Cijvat, Ellie
    Lund University.
    CMOS Integrated Switched-Mode Transmitters for Wireless Communication2010In: Advances in Solid State Circuits Technologies / [ed] Paul K Chu, INTECH, 2010Chapter in book (Other academic)
  • 4.
    Cijvat, Ellie
    Lund University.
    CMOS Transceiver Front-Ends in Mobile Communication Handsets: Architectures and Building Blocks2004Doctoral thesis, monograph (Other academic)
    Abstract [en]

    For mobile communication systems in the low-GHz range, CMOS has increasingly become the technology of choice, and the level of integration in mobile handsets has risen. The use of off-chip components, which increases the handset assembly time and costs, is preferably avoided. However, integrating a complete transceiver on a single chip leads to disturbances between building blocks. This imposes new and more stringent requirements on building block and transceiver performance, as well as impacts the choice of transceiver architecture.

    In the general introduction, an overview is given of front-end receiver and transmitter aspects as well as RF CMOS technology. This includes the impact of mobile communication system specifications on architectures and building blocks, transistor and monolithic inductor modeling, and disturbance issues. Special attention is given to power amplifiers, the most challenging building blocks in CMOS transceivers. Papers I, II and III address CMOS receiver front-end aspects and implementations, while in papers IV and V design and challenges of CMOS power amplifiers are described.

  • 5.
    Cijvat, Ellie
    et al.
    Lund University.
    Lundin, Rikard
    Lund University.
    Miljöföreläsningar med simulerad klimatkonferens i elektronikundervisning2009Other (Other (popular science, discussion, etc.))
  • 6.
    Cijvat, Ellie
    et al.
    Lund University.
    Lundin, Rikard
    Lund University.
    Miljöföreläsningar med simulerad klimatkonferens i elektronikundervisning2009In: Proceedings Utvecklingskonferens 09, Lunds universitet / [ed] Anders Sonesson, Gunilla Amnér, 2009, p. 185-192Conference paper (Other academic)
  • 7.
    Cijvat, Ellie
    et al.
    Lund University.
    Sjoland, Henrik
    Lund University.
    Two 130nm CMOS class-D RF power amplifiers suitable for polar transmitter architectures2008In: 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008., IEEE Press, 2008, p. 1380-1383Conference paper (Refereed)
    Abstract [en]

    Two class-D RF power amplifiers consisting of CMOS inverter chains have been designed and measured. The first amplifier operates at 1GHz and has a maximum output power of 12dBm, whereas the second operates at 1.5GHz and outputs a maximum of 6dBm. The amplifiers have been characterized for use in two different polar transmitter architectures, Pulse Width Modulation by Variable Gate Bias (PWMVGB) and Envelope Elimination and Restoration (EER). Using a standard 130nm digital CMOS process and off-chip passive components, maximum drain efficiencies of 32% and 39%, respectively, are achieved. The two amplifiers are compared with respect to output power and drain efficiency, including a qualitative analysis of losses. Moreover, their use in the two polar transmitter architectures is discussed.

  • 8.
    Cijvat, Ellie
    et al.
    Lund University.
    Sjöland, Henrik
    Lund University.
    A Fully Integrated 2.45 GHz 0.25 um CMOS Power Amplifier2003In: Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003, IEEE Press, 2003, p. 1094-1097Conference paper (Refereed)
    Abstract [en]

    A fully integrated differential class-AB power amplifier has been designed in a 0.25um CMOS technology. It is intended for medium output power ranges such as Bluetooth class I, and has an operating frequency of 2.45GHz. By using two parallel output stages that can be switched on or off, a high efficiency can be achieved for both high and low output power levels. The simulated maximum output power is 22.7 dBm, while the maximum power- added efficiency is 22%.

  • 9.
    Cijvat, Ellie
    et al.
    Lund University.
    Sjöland, Henrik
    Lund University.
    Tom, Kevin
    Victoria University.
    Faulkner, Mike
    Victoria University.
    A comparison of polar transmitter architectures using a GaN HEMT power amplifier2008In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008., IEEE Press, 2008, p. 1075-1078Conference paper (Refereed)
    Abstract [en]

    In this paper three transmitter architectures are compared, that each use the low-frequency envelope and high-frequency phase component of an RF signal. A power amplifier (PA) with Pulse Width Modulation by Variable Gate Bias (PWMVGB) is compared to an Envelope Elimination and Restoration (EER) and Envelope Tracking (ET) configuration. The test circuit is implemented using a discrete GaN HEMT power amplifier and discrete surface-mount passive components assembled on a PCB. Measurements show that the EER architecture maintains a drain efficiency of 56 to 69% for a wide output power range, while the PA with variable gate bias shows a significant drop in efficiency for lower output powers (from 59 to 6%). Other comparison issues are modulation of the supply voltage and transmitter complexity.

  • 10.
    Cijvat, Ellie
    et al.
    University of California, USA.
    Tadjpour, Shahrzad
    University of California, USA.
    Abidi, A.A.
    University of California, USA.
    Spurious mixing of off-channel signals in a wireless receiver and the choice of IF2002In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 49, no 8, p. 539-544Article in journal (Refereed)
    Abstract [en]

    Circuit nonlinearity and LO harmonics can cause large interferers to translate on to the same intermediate frequency as the desired channel. The mechanisms responsible for spurious mixing, which are distinct from intermodulation distortion, are analyzed and catalogued. The analysis leads to an optimal choice of IF for a fully integrated 900 MHz GSM receiver that resists all blockers.

  • 11.
    Cijvat, Ellie
    et al.
    Lund University.
    Tom, Kevin
    Victoria University, Australia.
    Faulkner, Mike
    Victoria University, Australia.
    Sjöland, Henrik
    Lund University.
    A GaN HEMT Power Amplifier with Variable Gate Bias for Envelope and Phase Signals2007In: Proceedings of Norchip 2007, Aalborg, Denmark, 2007, Aalborg, Denmark: Institute of Electrical and Electronics Engineers (IEEE), 2007Conference paper (Refereed)
    Abstract [en]

    This paper describes the design, simulation and measurement of a GaN power amplifier suitable for envelope and phase signal combination. The low-frequency envelope signal is used to vary the gate (bias) voltage of the device, resulting in a pulse width modulated drain voltage, while modulation of supply voltage or current is avoided. The test circuit is implemented using a discrete GaN HEMT power amplifier and discrete surface-mount passive components assembled on a PCB. Measurements showed a maximum drain efficiency of 59% at 360 MHz, at an output power of 29 dBm. The output power as a function of the gate bias voltage varied between 3 and 29 dBm, with the drain efficiency varying between 6 and 59%.

  • 12.
    Cijvat, Ellie
    et al.
    Lund University.
    Tom, Kevon
    Victoria University, Australia.
    Faulkner, Mike
    Victoria University, Australia.
    Sjöland, Henrik
    Lund University.
    Comparing polar transmitter architectures using a GaN HEMT power amplifier2008In: Abstracts book of The Gigahertz Symposium 2008: 5-6 March, 2008, Chalmers University of Technology, Göteborg, Sweden / [ed] Jan Grahn, Gothenburg: Chalmers University of Technology , 2008, p. 21-21Conference paper (Other academic)
    Abstract [en]

    A power amplifier (PA) with variable gate bias is compared to an Envelope Elimination and Restoration (EER) configuration. Each use the lowfrequency envelope and high-frequency phase component of the signal. The test circuit is implemented using a discrete GaN HEMT power device. Measurements show that the EER architecture maintains a relatively high drain efficiency for a wide output power range, while the PA with variable gate bias shows a significant drop in efficiency for lower output powers.

  • 13.
    Cijvat, Ellie
    et al.
    Lund University.
    Troedsson, Niclas
    Lund University.
    Sjöland, Henrik
    Lund University.
    A 2.4GHz CMOS Power Amplifier Using Internal Frequency Doubling2005In: IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005, Kobe, Japan: IEEE Press, 2005, p. 2683-2686Conference paper (Refereed)
    Abstract [en]

    A fully integrated 0.18 /spl mu/m 1P6M CMOS power amplifier using internal frequency doubling is presented. Two chips were measured, one stand-alone PA and one PA with a VCO on the same chip. Since the PA and VCO operate at different frequencies, this configuration is suitable for direct-upconversion or low-IF upconversion since oscillator pulling is reduced. The maximum output power is 15 dBm, and the maximum drain efficiency is 10.7% at an output operating frequency of 2.4 GHz.

  • 14.
    Tadjpour, Shahrzad
    et al.
    University of California, Los Angeles.
    Cijvat, Ellie
    University of California, Los Angeles.
    Hegazi, Emad
    University of California, Los Angeles.
    Abidi, A.A
    University of California, Los Angeles.
    A 900-MHz Dual-Conversion Low-IF GSM Receiver in 0.35 μm CMOS2001In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 36, no 12, p. 1992-2002Article in journal (Refereed)
    Abstract [en]

    A low-power fully integrated GSM receiver is developed in 0.35-μm CMOS. This receiver uses dual conversion with a low IF of 140 kHz. This arrangement lessens the impact of the flicker noise. The first IF of 190 MHz best tolerates blocking signals. The receiver includes all of circuits for analog channel selection, image rejection, and more than 100-dB controllable gain. The receiver alone consumes 22 mA from a 2.5-V supply, to give a noise figure of 5 dB, and input IP3 of -16 dBm. A single frequency synthesizer generates both LO frequencies. The integrated VCO with on-chip resonator and buffers consume another 8 mA, and meet GSM phase-noise specifications.

1 - 14 of 14
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  • ieee
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